1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register which is capable of performing bi-directional scanning.
2. Discussion of the Related Art
Recently, various flat panel display devices have appeared on the market to overcome disadvantages of a cathode ray tube (CRT), such as weight, volume, etc. Such flat display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and a light emitting display (LED), etc.
A related art LCD displays images thereon as light transmitted to the liquid crystal layer is controlled using electric fields. Here, the LCD includes a LCD panel in which liquid crystal (LC) cells are aligned in matrix form and a drive circuit for driving the LCD panel. The LCD panel comprises gate lines and data lines crossing each other therein. Liquid crystal (LC) cells are defined by the crossed regions. More specifically, the LCD panel includes pixel electrodes and common electrodes to apply electric fields to the respective LC cells. The pixel electrodes are connected to the data lines via sources and drains of the thin film transistor (TFT) which function as switching elements, respectively. The gate of the TFT is connected to one of the gate lines. The TFT for an LCD panel uses amorphous silicon or polysilicon in the semiconductor layer. Amorphous LCD apparatus has advantages in that the amorphous silicon layer has relatively good uniformity and stable characteristics. On the other hand, the amorphous LCD apparatus has drawbacks in that it is difficult to enhance the pixel density since it has relatively small charge mobility. However, such a problem can be overcome by improving the circuitry of the LCD apparatus such that a driving circuit using amorphous silicon is embedded on an array substrate.
As shown in FIG. 1, the LCD apparatus of the related art includes an image display 12 for displaying images, an LCD panel 10 for providing gate pulses to the image display 12, in which the image display 12 forms a gate shift register 50 therein, a printed circuit board (PCB) 20 on which a control circuit and a power supply circuit are mounted, a plurality of tape carrier packages (TCP) 30 which are connected between the PCB 20 and the LCD panel 10, and a plurality of data integrated circuits (ICs) 40 for providing analog image signals to the image display 12, wherein the data ICs 40 are mounted on each TCP 30. The image display 12 displays images through LC cells which are formed in a matrix form. Each LC cell is a switching element connected to a node between a gate line GL and a data line DL. Each LC cell includes TFTs which are formed of polysilicon or amorphous silicon. The data line DL inputs analog image signals from the data IC 40. The gate line GL inputs the gate pulses from the gate shift register 50.
Each image TCP 30 is electrically connected between the PCB 20 and the LCD panel 10 in a tape automated bonding (TAB) fashion. The input pads of each TCP 30 are electrically connected to the PCB 20 and the output pads are electrically connected to the LCD panel 10. Control signals and data signals from the control circuit mounted on the PCB 20 is input to each data IC 40 through the input pads of the TCP 30. Then the data IC 40 converts the data signals to analog image signals, using the input control signal, and provides the analog image signals to the data line DL of the LCD panel 10 through the output pads of the TCP 30.
As shown in FIG. 2, the gate shift register 50 is directly formed at one side of the LCD panel 10. The gate shift register 50 includes a plurality of stages 511˜51n whose output leads are connected to the gate lines GL, respectively. The plurality of stages 511˜51n are connected to a start pulse input line to which a start pulse SP is provided, respectively, and connected to at least one of clock signal input lines to which clock signals CLK are provided, in which the clock signals are sequentially phase-delayed by one clock. For example, if two clock signals are provided to the clock signal input lines, the gate shift register 50 is referred to as a “two-phase shift register.” Therefore, the respective stages 511˜51n shift the start pulse by one clock using one of the clock signals, and then output one clock-shifted start pulse thereto. The output signals from the respective stages 511˜51n of the gate shift register 50 are functioned as gate pulses GP, and, at the same time, the output signals from stages 511˜51n-1 are provided to the next stage 512˜51n, to function as a start pulse SP.
As mentioned above, the LCD apparatus of the related art provides analog image signals from the plurality of data ICs 40 to the data lines DL, and the gate pulses GP are synchronously and sequentially provided to the gate lines GL, using the gate shift register 50 installed in the LCD panel 10. Therefore, the image display 12 can display images thereon. Namely, the LCD apparatus of the related art is triggered by a single start pulse SP to transfer an output signal to a next stage, such that the gate pulses can be sequentially output to the gate lines GL. Therefore, the LCD apparatus can only output the output signals uni-directionally. In other words, it cannot perform bi-directional scanning.